Capacitors on a semiconductor basis are utilized in various integrated circuits such as, for example, dynamic memory cell arrangements, analog-to-digital and digital-to-analog converters as well as filter circuits. The problem of reducing the space requirement of the capacitor given unchanged capacitance must be solved in the manufacture of capacitors on a semiconductor basis in view of an increased integration density or reduced chip area.
The problem is especially serious in dynamic semiconductor memories wherein the required area of the generally employed single-transistor memory cell is being reduced from memory generation to memory generation with increasing memory density. At the same time, a certain minimum capacitance of the storage capacitor must be preserved.
A single-transistor memory cell of a dynamic semiconductor memory arrangement (DRAM memory arrangement) comprises a readout transistor and a capacitor. The information is stored in the capacitor in the form of an electrical charge that represents a logical quantity, 0 or 1. This information can be read out via a bit line by driving the readout transistor via a word line. The capacitor must comprises a minimum capacitance for reliable storage of the charge and, at the same time, distinguishability of the information read out. The lower limit for the capacitance of the storage capacitor is currently considered to be at 25 fF.
Up to the 1 Mbit generation, both the readout transistor as well as the capacitor were realized as planar components. Beginning with the 4 Mbit memory generation, a further reduction in the area of the memory cell was achieved by a three-dimensional arrangement of readout transistor and storage capacitor. One possibility therefor is comprised in realizing the storage capacitor in a trench (see, for example, B. K. Yamada et al., Proc. Intern. Electronic Devices and Material, IEDM 85, pp. 702 ff.). In this case, the electrodes of the storage capacitor are arranged along the surface of the trench. As a result thereof, the effective area of the storage capacitor, on which the capacitance is dependent, is enlarged compared to the space requirement at the surface of the substrate for the storage capacitor that corresponds to the crossection of the trench.
Another possibility for increasing the storage capacity given unchanged or reduced space requirement of the storage capacitor is comprised in implementing the storage capacitor as stacked capacitor. A structure of polysilicon, for example a crown structure or a cylinder, that is contacted with the substrate is thereby formed over the word lines. This polysilicon structure forms the storage node. It is provided with capacitor dielectric and capacitor plate. This design has the advantage that it is largely compatible with a logic process. The free space above the substrate surface is used for the storage capacitor. The entire cell area can thereby be covered by the polysilicon structure as long as the polysilicon structures for neighboring memory cells are insulated from one another.
European reference EP 0 415 530 B1 discloses a memory cell arrangement with a stacked capacitor as storage capacitor. The stacked capacitor comprises a polysilicon structure with a plurality of polysilicon layers arranged essentially parallel above one another that are connected to one another via at least one lateral support. These layers arranged like cooling ribs lead to a clear enlargement of the surface of the polysilicon structure compared to the projection of the polysilicon structure onto the substrate surface. The polysilicon structure is formed by alternating deposition of polysilicon layers and SiO.sub.2 layers etchable selectively thereto on the surface of the substrate, structuring these layers, formation of the lateral support and selecting etching the SiO.sub.2 layers out. The polysilicon structures are thereby arsenic-doped. Subsequently, silicon oxide is formed as capacitor dielectric by thermal oxidation, a cell plate of doped polysilicon being deposited thereon. The required mechanical stability of the polysilicon layers arranged parallel and the fact of having to introduce the capacitor dielectric and the cell plate between polysilicon layers arranged parallel limit the possible enlargement of the surface.
For enlarging the surface of a capacitor electrode, U.S. Pat. No. 5,254,503 has proposed that this be structured with the assistance of a mask of polysilicon nuclei that are formed by CVD deposition or with the assistance of a mask that was formed upon utilization of surface roughness. The structures in the mask are statistical in size and density, so that the enlargement of the surface and, thus, the achievable capacitance are difficult to control.